The present invention relates to a control circuit for a DC-DC converter, and a semiconductor device, a DC-DC converter, and an electronic device.
A portable electronic device, such as a notebook personal computer, typically has an incorporated battery, which functions as a power supply for the device. The portable electronic device also has a built-in DC-DC converter. The DC-DC converter charges the battery with an external power supply, such as an AC adapter, which is connected to the portable electronic device. In many cases, a DC-DC converter used to perform charging, such as a DC-DC converter of constant voltage, constant current control type, which controls its output using a plurality of control signals (two control signals for constant voltage control and constant current control in this case). The present invention relates to a preferred structure for such a DC-DC converter that controls output using a plurality of control signals.
Japanese Patent No. 3405871 describes one example of this type of DC-DC converter. FIG. 1 is a schematic block diagram describing a conventional constant voltage, constant current control type DC-DC converter of Japanese Patent No. 3405871.
A DC-DC converter 1 includes a control circuit 2 for controlling the entire DC-DC converter 1. The control circuit 2 is provided with an operation signal ON for instructing start and stop operations for the DC-DC converter 1. The DC-DC converter 1 starts operating when the operation signal ON is high and stops operating when the operation signal ON is low.
The DC-DC converter 1 includes transistors Tr1 and Tr2, a coil L1, a diode D1, and capacitors C1 and C2. The transistor Tr1, which is connected to the control circuit 2, functions as a main switching transistor. The transistor Tr1, which receives a drive signal SG1 from the control circuit 2, is controlled so that it goes on and off in accordance with the drive signal SG1. The coil L1 is a choke coil for converting voltage. The transistor Tr2, which is connected to the control circuit 2, functions as a synchronous rectifier switch. The transistor Tr2 goes on when the transistor Tr1 is off to discharge the energy accumulated in the coil L1. The transistor Tr2, which receives a drive signal SG2 from the control circuit 2, is controlled to go on and off in accordance with the drive signal SG2. The diode D1 is formed by a flywheel diode connected to the coil L1. In the same manner as for the transistor Tr2, the diode D1 goes on when the transistor Tr1 is off to discharge the energy accumulated in the coil L1.
The capacitor C1 is a smoothing capacitor for smoothing the output of the DC-DC converter 1. A resistor Rs is connected to an output terminal 1a of the DC-DC converter 1. The resistor Rs is a current sense resistor, which is used to detect an output current Io of the DC-DC converter 1. A battery BT, which is a secondary battery, is connected to the output terminal 1a of the DC-DC converter 1. The capacitor C2 is connected between the control circuit 2 and the ground GND. The capacitor C2 is a soft start control capacitor, which suppresses generation of an inrush current from an input (input voltage Vi) during activation of the DC-DC converter 1. The input voltage Vi is a direct current voltage provided from an AC adaptor (not shown), which is connected to the DC-DC converter 1.
The control circuit 2 includes a voltage amplification circuit 3, first and second error amplification circuits 4 and 5, a PWM (pulse-width modulation) comparison circuit 6, a triangular waveform oscillator circuit 7, first and second output circuits 8 and 9 (Drv1 and Drv2 in the figure), and a power supply circuit 10.
The power supply circuit 10 controls the entire DC-DC converter 1 so that it goes on and off by controlling the supply of power to the entire control circuit 2 in accordance with an operation signal ON, which is provided from an external device. Resistors R1 and R2 are voltage dividing resistors for dividing an output voltage Vo of the DC-DC converter 1. The resistors R1 and R2 divide the output voltage Vo to generate voltage (divisional voltage) that is supplied to an inversion input terminal of the first error amplification circuit 4.
The first error amplification circuit 4 amplifies the voltage difference between the divisional voltage of the output voltage Vo supplied to the inversion input terminal and a reference voltage e1 supplied to the non-inversion input terminal. Then, the first error amplification circuit 4 supplies the amplified voltage to the PWM comparison circuit 6. The resistances of the resistors R1 and R2 are set so that the divisional voltage generated by the resistors R1 and R2 is equal to the reference voltage e1 when the value of the output voltage Vo of the DC-DC converter 1 is a value determined by a constant voltage operation of the DC-DC converter 1 (e.g., 12.6 V).
The voltage amplification circuit 3 is connected to the current sense resistor Rs. The voltage amplification circuit 3 amplifies voltage between the two terminals of the resistor Rs, which is generated by a current (i.e., an output current Io of the DC-DC converter 1) flowing through the current sense resistor Rs, and supplies the amplified voltage to an inversion input terminal of the second error amplification circuit 5. The second error amplification circuit 5 amplifies the voltage difference between the output voltage of the voltage amplification circuit 3 supplied to its inversion input terminal and a reference voltage e2 supplied to its non-inversion input terminal. The second error amplification circuit 5 then supplies the amplified voltage to the PWM comparison circuit 6. The reference voltage e2 is set in correspondence with the value (e.g., 3 A) of the output current Io determined by a constant current operation of the DC-DC converter 1.
The transistor Tr3, which is connected to the power supply circuit 10 and the capacitor C2, is controlled so that it goes on and off by the power supply circuit 10 in accordance with the operation signal ON. The transistor Tr3 is a switch circuit, which discharges charge accumulated in the capacitor C2 and sets the potential of the capacitor C2 to 0 V when the DC-DC converter 1 is not functioning. A constant current circuit 11 is connected to the transistor Tr3 and the capacitor C2. The constant current circuit 11 functions as a charging circuit, which charges the capacitor C2 and raises the potential of the capacitor C2 when the transistor Tr3 is off.
The PWM comparison circuit 6 has a first non-inversion input terminal connected to the first error amplification circuit 4, a second non-inversion input terminal connected to the second error amplification circuit 5, a third non-inversion input terminal connected to the capacitor C2, and an inversion input terminal connected to the triangular waveform oscillator circuit 7. The PWM comparison circuit 6 is a pulse width modulation circuit. In detail, the PWM comparison circuit 6 compares the lowest one of the voltages supplied to its non-inversion input terminals with the voltage provided to its inversion input terminal. Based on the comparison result, the PWM comparison circuit 6 outputs pulses when the voltage provided to the non-inversion input terminal is higher than the voltage provided to the inversion input terminal. The inversion input terminal of the PWM comparison circuit 6 is provided with a triangular waveform signal OSC1, which is oscillated at a constant frequency, from the triangular waveform oscillator circuit 7. The first non-inversion input terminal of the PWM comparison circuit 6 is provided with an output signal ERA1 of the first error amplification circuit 4. The second non-inversion input terminal is provided with an output signal ERA2 of the second error amplification circuit 5. The third non-inversion input terminal is provided with voltage between the two terminals of the capacitor C2 (soft start signal SS), which rises when the constant current circuit 11 performs charging.
The first output circuit 8 is connected to the PWM comparison circuit 6 and the transistor Tr1. The first output circuit 8 sets the transistor Tr1 to the on state when it is receiving pulses from the PWM comparison circuit 6. The second output circuit 9 is connected to the PWM comparison circuit 6 and the transistor Tr2. The second output circuit 9 is controlled by an output of the PWM comparison circuit 6. The second output circuit 9 sets the transistor Tr2 to the on state when the transistor Tr1 is off.
The DC-DC converter 1 feeds back the control circuit 2 with a detection result of the output voltage Vo and the output current Io to control an output pulse width of the PWM comparison circuit 6 (PWM control). In this way, the DC-DC converter 1 controls the output voltage Vo and the output current Io by controlling a ratio of an on-time Ton and an off-time Toff (on-off ratio) of the transistor Tr1.
The constant voltage operation and the constant current operation of the DC-DC converter 1 will now be described.
First, the constant voltage operation of the DC-DC converter 1 will be described, with reference to FIG. 2. The constant voltage operation is an operation mode for controlling the DC-DC converter 1 so that its output voltage Vo is maintained at a constant voltage (e.g., 12.6 V).
During the constant voltage operation of the DC-DC converter 1, voltage (divisional voltage) generated by the resistors R1 and R2 dividing the output voltage Vo is close to the reference voltage e1. During the constant voltage operation, the output current Io is smaller than current determined by the constant current operation, which will be described later. Thus, voltage generated by the voltage amplification circuit 3, which amplifies voltage generated from the current Io flowing through the current sense resistor Rs, is substantially smaller than the reference voltage e2. As a result, the output voltage of the second error amplification circuit 5 rises to as high as a value close to a maximum value. To be specific, the voltage of the output signal ERA2 of the second error amplification circuit 5 is higher than the voltage of the output signal ERA1 of the first error amplification circuit 4 as shown in FIG. 2. Thus, during the constant voltage operation, the PWM comparison circuit 6 controls its output pulses according to the output signal ERA1 of the first error amplification circuit 4.
Next, the constant current operation of the DC-DC converter 1 will be described, with reference to FIG. 3. The constant current operation is an operation mode for controlling the DC-DC converter 1 to have its output current Io maintained at a constant current (e.g., 3 A here).
During the constant current operation of the DC-DC converter 1, voltage generated by the voltage amplification circuit 3 amplifying voltage generated from the current (output current Io) flowing through the current sense resistor Rs is close to the reference current e2. During the constant current operation, the output voltage Vo is smaller than voltage determined by the constant voltage operation, which is described above. Thus, voltage generated by the resistors R1 and R2 dividing the output voltage Vo is substantially smaller than the reference voltage e1. As a result, the output voltage of the first error amplification circuit 4 rises to as high as a value close to a maximum value. To be specific, the voltage of the output signal ERA1 of the first error amplification circuit 4 is higher than the voltage of the output signal ERA2 of the second error amplification circuit 5 as shown in FIG. 3. Thus, during the constant current operation, the PWM comparison circuit 6 controls its output pulses according to the output signal ERA2 of the second error amplification circuit 5.
Next, the activation operation of the DC-DC converter 1 will be described.
When the DC-DC converter 1 is activated, the transistor Tr3 is turned off by the power supply circuit 10, and the capacitor C2 is charged by the constant current circuit 11. The voltage of the soft start signal SS gradually rises from 0 V as the capacitor C2 is charged. During activation of the DC-DC converter 1, the values of the output voltage Vo and the output current Io of the DC-DC converter 1 are substantially smaller than values determined by the reference voltages e1 and e2, respectively. Thus, voltage difference between the voltage (divisional voltage) generated by the resistors R1 and R2, which divide the output voltage Vo, and the reference voltage e1 is substantially maximum. Further, voltage difference between the output voltage of the voltage amplification circuit 3, which is generated by amplifying the voltage between the two terminals of the current sense resistor Rs, and the reference voltage e2 is substantially maximum. In other words, the voltages of the output signals ERA1 and ERA2 of the first and second error amplification circuits 4 and 5 are substantially maximum when activating the DC-DC converter 1.
The PWM comparison circuit 6 controls its output pulse width based on the one of these signals (SS, ERA1, and ERA2) having the lowest potential. To be specific, the PWM comparison circuit 6 outputs pulses having a pulse width proportional to the voltage of the soft start signal SS during activation of the DC-DC converter 1.
During activation of the DC-DC converter 1, the output voltages of the first and second error amplification circuits 4 and 5 are maximum. When assuming that the PWM comparison circuit 6 controls its output pulse width according to the output signal ERA1 or ERA2, the output pulse width is maximum (i.e., the on-time Ton of the transistor Tr1 is maximum), and an excessive current (inrush current) flows through the DC-DC converter 1. However, the PWM comparison circuit 6 actually controls its output pulse width according to the soft start signal SS during activation of the DC-DC converter 1 as described above. This suppresses generation of an excessive current (inrush current) from an input, which would otherwise flow through the DC-DC converter 1.
In other words, the DC-DC converter 1 uses the soft start signal SS during activation to limit the output pulse width of the PWM comparison circuit 6 and to shorten the on-time Ton of the transistor Tr1. This suppresses generation of an inrush current. After the voltage of the soft start signal SS rises as the capacitor C2 is charged until the output voltage Vo or the output current Io of the DC-DC converter 1 reaches its specified value, the DC-DC converter 1 executes constant voltage control in the above-described constant voltage mode, or constant current control in the above-described constant current mode.
However, the conventional DC-DC converter 1 described above has a shortcoming in that the DC-DC converter 1 fails to suppress generation of an inrush current when the control of its output (PWM control) is switched from the control using the soft start signal SS to the control using the output signal ERA1 of the first error amplification circuit 4 (constant voltage control) or to the control using the output signal ERA2 of the second error amplification circuit 5 (constant current control).
The generation of an inrush current will now be described with reference to FIG. 4.
FIG. 4 shows an operational waveform during activation of the DC-DC converter 1. First, the DC-DC converter 1 is activated at time t1. Then, the voltages of the output signals ERA1 and ERA2 of the first and second error amplification circuits 4 and 5 are set substantially at the maximum voltage Vmax.
The voltage of the soft start signal SS gradually rises from 0 V as the capacitor C2 is charged. The voltage of the soft start signal SS finally exceeds the voltage of the triangular waveform signal OSC1 at time t2. Then, the PWM comparison circuit 6 outputs pulses having a pulse width according to the voltage of the soft start signal SS. Afterwards, the output voltage Vo and the output current Io of the DC-DC converter 1 gradually rise in proportion to the on-time Ton of the transistor Tr1, which is controlled to go on and off by the output pulses of the PWM comparison circuit 6.
At time t3, the output current Io reaches the value (e.g., 3 A here) determined by the constant current operation (specifically, the output voltage of the voltage amplification circuit 3 reaches the reference voltage e2). Then, the voltage of the output signal ERA2 of the second error amplification circuit 5 falls to a control voltage Vct for maintaining the output current Io at a constant current of 3 A.
However, the voltage of the output signal ERA2 in this state does not reach the control voltage Vct immediately. The voltage of the output signal ERA2 falling from the maximum voltage Vmax to the control voltage Vct requires a response delay time according to an RC (resistance-capacitance) time constant, which is set for the second error amplification circuit 5 (time indicated by t4-t3 in FIG. 4).
The voltage of the soft start signal SS continues to rise from when the voltage of the output signal ERA2 starts falling to when the voltage of the output signal ERA2 reaches the control voltage Vct. This extends the on-time Ton of the transistor Tr1 so that the output voltage Vo continues to rise further. As a result, an inrush current is generated (i.e., the output current Io larger than the current (3 A) determined by the control voltage Vct is generated) in a period from when the voltage of the output signal ERA2 starts falling to when the DC-DC converter 1 switches to the constant current control (i.e., to when the voltage of the output signal ERA2 reaches the control voltage Vct).
Such an inrush current is generated not only when the output control of the DC-DC converter 1 (PWM control) is switched from the control using the soft start signal SS to the constant current control, but also when the output control is switched from the control using the soft start signal SS to the constant voltage control. In this way, the conventional configuration fails to suppress generation of an inrush current during activation of the DC-DC converter.